RISC-V CPU Core (RV32I)

Overview

A custom RISC-V processor built from scratch in Verilog, implementing the RV32I base integer instruction set three separate ways: a single-cycle design, a multi-cycle design, and a fully pipelined 5-stage implementation (fetch, decode, execute, memory access, write-back). The pipelined version handles data hazards through forwarding and stalling, with optional branch prediction and a synchronous RAM memory interface. The codebase is kept modular to make future extensions — multiplication/division support, cache integration, formal verification — straightforward to add.

Highlights

• Three implementations of the same RV32I core: single-cycle, multi-cycle, and 5-stage pipelined
• Pipeline hazard handling via forwarding and stalling across all five stages
• Optional branch prediction and a synchronous RAM memory interface
• Testbenches and documentation included; cache integration and formal verification are on the roadmap

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