Sequential Logic & Synchronous Design

Combinational logic alone can't build a counter or a register, because there's no way to retain state between clock cycles. That requires a latch or flip-flop.

Sequential logic: adding memory

A D flip-flop is the workhorse of synchronous design: on the rising edge of the clock, it copies its data input (D) to its output (Q) and holds that value until the next edge.

       ___________
D ----|           |
      | D     Q   |---- Q
CLK --|>          |
      |___________|

Chaining flip-flops gives you registers; feeding a flip-flop's output back through combinational logic into its own input gives you counters and state machines.

Why synchronous design dominates

Real circuits are built as synchronous systems: every flip-flop shares a common clock, and all state updates happen on the same edge. This avoids race conditions that plague purely asynchronous logic, at the cost of a maximum clock frequency determined by the slowest combinational path between two flip-flops — the critical path.

max frequency ≈ 1 / (critical path delay + flip-flop setup time)

This single inequality is why timing closure is such a central concern in both ASIC and FPGA design: every nanosecond of unnecessary combinational delay on the critical path directly caps your clock speed.

From gates to a CPU

A CPU's datapath — the ALU, register file, and program counter — is built entirely from the combinational and sequential building blocks covered in this lesson. Understanding gates and flip-flops at this level is what makes a CPU's fetch-decode-execute cycle legible rather than a black box, and it's the foundation the rest of the Computer Engineering Fundamentals roadmap builds on.